Table of Contents
Advertisement
Designing Your Target System's Emulator Connector (14-Pin Header) / Bus Protocol / IEEE 1149.1 Standard
15.2 Bus Protocol
15.3 IEEE 1149.1 Standard
Designing Your Target System's Emulator Connector (14-Pin Header)
Although you can use other headers, recommended parts include:
straight header, unshrouded
The IEEE 1149.1 specification covers the requirements for the test access port
(TAP) bus slave devices and provides certain rules, summarized as follows:
The TMS/TDI inputs are sampled on the rising edge of the TCK signal of
the device.
The TDO output is clocked from the falling edge of the TCK signal of the
device.
When these devices are daisy-chained together, the TDO of one device has
approximately a half TCK cycle setup to the next device's TDI signal. This type
of timing scheme minimizes race conditions that would occur if both TDO and
TDI were timed from the same TCK edge. The penalty for this timing scheme
is a reduced TCK frequency.
The IEEE 1149.1 specification does not provide rules for bus master (emula-
tor) devices. Instead, it states that it expects a bus master to provide bus slave
compatible timings. The XDS510 provides timings that meet the bus slave
rules.
For more information concerning the IEEE 1149.1 standard, contact IEEE
Customer Service:
Address: IEEE Customer Service
445 Hoes Lane, PO Box 1331
Piscataway, NJ 08855-1331
Phone:
(800) 678–IEEE in the US and Canada
(908) 981–1393 outside the US and Canada
FAX:
(908) 981–9667
DuPont Connector Systems
part numbers:
Telex:
833233
Designing for JTAG Emulation
65610–114
65611–114
67996–114
67997–114
15-3
Advertisement
Chapters
Table of Contents
