Texas Instruments TMS320C6201 Reference Manual page 469

direct mapped cache diagram 4-7
flush word count register fields 4-8
L1P address allocation 4-6
L1P cache direct mapped 4-2
L1PFWC register 4-8
L2
access 4-13
cache data request flow chart, figure 4-17
description 4-13
interfaces 4-15
memories 4-15
memory configuration, figure 4-14
operation 4-15
L2 CE Space Allocation Register Fields,
figure 4-18, 4-19, 4-20
L2 clean base address register fields, figure 4-23
L2 clean register 4-5
L2 clean register fields description 4-22
L2 controller 1-7
L2 EDMA Service 4-21
L2 flush 4-21
L2 Flush Base Address Register Fields,
figure 4-22
L2 flush register 4-5
L2 Flush Register Fields 4-22
L2 flush register fields 4-22
L2 Flush Word Count Register Fields, figure 4-23
L2 invalidation 4-21
L2ALLOC Bit Function, table 4-20
L2CBAR register 4-23
L2FBAR register 4-22
L2FWC register 4-22
latching 5-18
least recently used (LRU) 4-9
least–significant address bit 9-14
level 1 data cache mode settings 4-10
level 1 program cache mode settings 4-6
level–one data cache (L1D) controller 1-7
level–one program cache (L1P) 1-7
line/frame count (FC) 6-12
line/frame index (FIX) 6-12
link address 6-16
LINK bit in the options field 6-25
Link Conditions, table 6-26
Linked EDMA Transfer, figure 6-25
linking EDMA transfers 6-25
linking events 6-13
little endian (LE) 7-8
lock–up or error condition 6-7
logical address bit 0 9-14
logical addressing 8-10
LSB address bits 7-8
M
manual start operation 5-13
map, of cache address 2-5
mapping, default interrupt 13-9
MAR register 4-18
maximum frame frequency 11-35
maximum frame frequency transmit receive,
figure 11-36
maximum number of elements in a frame 6-28
McBSP CPU interrupts and DMA synch 11-7
McBSP data 10-7
McBSP standard operation, figure 11-34
memory
access through the HPI during reset 7-27
address register (BISA) 8-35
CPU 7-2
data 1-6
first level 4-1
internal 1-6, 3-6, 4-1
internal memory configuratins 4-2
internal program 2-3
L2 configuration 4-14
L2 memory banks 4-2
map 5-12
program 1-6
program memory controller block diagram 3-3
range 3-7
second level 4-1
summary of 'C6202 memory map 10-6
TMS320C6000, internal configurations 3-2
TMS320C6201 3-2
TMS320C6202 3-2
TMS320C6211 memory map summary 10-7
two–level internal 4-1
memory architecture 4-1
memory attribute register 4-5
memory attribute register (MARs) 4-18
Index
Index-11