Texas Instruments TMS320C6201 Reference Manual page 377

Figure 11–40. CLKG Synchronization and FSG Generation When GSYNC = 1
and CLKGDV = 1
CLKS (CLKSP = 1)
CLKS (CLKSP = 0)
FSR external (FSRP = 0)
FSR external (FSRP = 1)
CLKG (no need to resync)
CLKG (needs resync)
FSG
Figure 11–41. CLKG Synchronization and FSG Generation When GSYNC = 1
and CLKGDV = 3
CLKS (CLKSP = 1)
CLKS (CLKSP = 0)
FSR external (FSRP = 0)
FSR external (FSRP = 1)
CLKG (no need to resync)
CLKG (needs resync)
FSG
Programmable Clock and Framing
Multichannel Buffered Serial Ports 11-59