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SPI Protocol: CLKSTP
11.7.2 McBSP Operation as the SPI Slave
When the McBSP is an SPI slave device, the master clock CLKX and slave
enable FSX are generated by an external SPI master, as shown in
Figure 11–53. Thus, the CLKX and FSX pins are configured as inputs by set-
ting the CLKXM and FSXM fields to zero in the PCR. In SPI mode, the FSX
and CLKX inputs are also utilized as the internal FSR and CLKR signals for
data reception. Data transfer is synchronized to the master clock CLKX and
the internal serial port logic performs transfers using only the exact number of
input clock pulses CLKX per data bit. The external master needs to assert FSX
(low) before the transfer of data begins. FSX is used in its asynchronous form
and it controls the McBSP's initial drive of data to the DX pin.
When the McBSP is a slave, (R/X)DATDLY in the receive/transmit control
register ((R/X)CR) should be set to zero. XDATDLY = 0 ensures that the first
data to be transmitted is available on the DX pin. The MISO waveform in
Figure 11–54 and Figure 11–55 shows how the McBSP transmits data as an
SPI slave. Setting RDATDLY = 0 ensures that the McBSP is ready to receive
data from the SPI master as soon as it detects the serial clock CLKX. Depend-
ing on the clock stop mode used, data is received at various clock edges ac-
cording to Table 11–21.
Although the CLKX signal is generated externally by the master, the internal
sample rate generator of the McBSP must be enabled for proper SPI slave
mode operation. The internal sample rate clock is then used to synchronize
the input clock (CLKX) and frame sync (FSX) from the master to the CPU
clock. Accordingly the CLKSM field of the sample rate generator (SRGR)
should be left at the default value (CLKSM = 1) to specify the CPU clock as the
clock source of the sample rate generator. Furthermore, the CLKGDV in the
SRGR must be set to a value such that the rate of the internal clock CLKG is
at least eight times that of the SPI data rate. This rate is achieved by program-
ming the sample rate generator to its maximum speed (CLKGDV = 1) for all
SPI transfer rates.
Multichannel Buffered Serial Ports
11-85
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