Texas Instruments TMS320C6201 Reference Manual page 160

EDMA Interrupt Generation
6.13.1 EDMA Interrupt Servicing by the CPU
6.13.2 Chaining EDMA Channels by an Event
6-34
Since the EDMA controller is aware when the EDMA channel transfer is com-
plete, it sets the appropriate bit in the CIPR as per the TCC specified by the
user. The CPU ISR should read the CIPR and determine what, if any events/
channels have completed and perform the operations necessary. The ISR
should clear the bit in CIPR upon servicing the interrupt, therefore enabling
recognition of further interrupts. Writing a '1' to the relevant bit can clear CIPR
bits, writing a '0' has no effect.
By the time one interrupt is serviced, many others could have occurred and
relevant bits set in CIPR. Each of these bits in CIPR would probably need dif-
ferent types of service, and therefore the ISR continues until all the posted in-
terrupts are serviced.
Four of the user-specified 4-bit transfer complete codes (TCC values 8, 9, 10,
and 11) can be used to trigger another EDMA channel transfer. The purpose
of these events triggering an EDMA transfer is to provide the user the ability
to chain several EDMA channels from one event that is driven by a peripheral
or external device (see Table 6–4).
To enable the EDMA controller to chain channels by way of a single event, the
TCINT bit must be set to '1'. Additionally, the relevant bit in the channel chain
enable register (CCER) in Figure 6–16 should be set to trigger off the next
channel transfer specified by TCC. Since events 8 to 11 are the only EDMA
channels that support chaining, only these bits are implemented in CCER.
Reading unused bits returns a '0' and writing to them has no effect. Therefore,
one can still specify a TCC value between 8 and 11, and need not necessarily
initiate the transfer on channels 8-11. However, the event is still captured in the
ER[11:8] even if the corresponding bit in CCER is disabled. This allows selec-
tive enabling and disabling of these 4 specific events.