Table of Contents
Advertisement
www.ti.com
1
2
MMCSD1_DAT[1]/
SATA_TXP
SATA_TXN
J
MMCSD1_DAT[3]/
SATA_VSS
SATA_VSS
H
PRU0_R30[25]/
PRU0_R30[24]/
MMCSD1_DAT[0]/
MMCSD1_CLK/
UPP_CHB_CLOCK/
UPP_CHB_START/
UPP_CHB_WAIT/
G
GP8[15]/
GP8[14]/
PRU1_R31[27]
PRU1_R31[26]
MMCSD1_DAT[6]/
MMCSD1_DAT[7]/
LCD_MCLK/
ECAP0_APWM0/
LCD_PCLK/
PRU1_R30[6]/
F
PRU1_R30[7]/
GP8[10]/
GP8[11]
PRU1_R31[7]
AXR1/
AXR2/
DX0/
DR0/
E
GP1[9]/
GP1[10]/
MII_TXD[1]
MII_TXD[2]
AXR7/
AXR4/
EPWM1TZ[0]/
FSR0/
PRU0_R30[17]
D
GP1[12]/
GP1[15]/
MII_COL
PRU0_R31[7]
AXR6/
CLKR0/
AFSR/
GP1[14]/
GP0[13]/
C
MII_TXEN/
PRU0_R31[20]
PRU0_R31[6]
ACLKX/
AFSX/
PRU0_R30[19]/
GP0[12]/
B
GP0[14]/
PRU0_R31[19]
PRU0_R31[21]
AHCLKR/
ACLKR/
PRU0_R30[18]/
USB_REFCLKIN/
PRU0_R30[20]/
UART1_RTS
/
A
GP0[15]/
GP0[11]/
PRU0_R31[22]
PRU0_R31[18]
1
2
3.6
Pin Multiplexing Control
Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.
For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed
with several different functions has a corresponding 4-bit field in one of the PINMUX registers.
Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data
and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'
of the peripheral functions in which case the pin's IO buffer is held tri-stated.
Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX
registers have no effect on input from a pin.
Copyright © 2010–2014, Texas Instruments Incorporated
3
4
5
VP_CLKIN3/
PRU0_R30[23]/
MMCSD1_CMD/
PRU1_R30[1]/
UPP_CHB_ENABLE/
DV
DD3318_C
GP6[2]/
GP8[13]/
PRU1_R31[2]
PRU1_R31[25]
VP_CLKIN2/
MMCSD1_DAT[5]/
LCD_HSYNC/
PRU1_R30[3]/
PRU1_R30[5]/
DV
DD3318_A
GP6[4]/
GP8[9]/
PRU1_R31[4]
PRU1_R31[6]
PRU0_R30[22]/
MMCSD1_DAT[4]/
PRU1_R30[8]/
LCD_VSYNC/
DV
PRU1_R30[4]/
DD3318_A
GP8[12]/
GP8[8]/
PRU1_R31[24]
PRU1_R31[5]
AXR0/
RTC_ALARM/
UART2_CTS
/
DV
GP8[7]/
DD3318_A
GP0[8]/
MII_TXD[0]/
DEEPSLEEP
CLKS0
AXR8/
AXR3/
CLKS1/
FSX0/
ECAP1_APWM1/
RV
DD
GP1[11]/
GP0[0]/
MII_TXD[3]
PRU0_R31[8]
AMUTE/
AXR5/
AXR10/
PRU0_R30[16]/
CLKX0/
DR1/
UART2_RTS/
GP1[13]/
GP0[2]
GP0[9]/
MII_TXCLK
PRU0_R31[16]
AXR9/
AXR12/
AXR11/
DX1/
FSR1/
FSX1/
GP0[1]
GP0[4]
GP0[3]
AXR13/
AXR14/
EMA_D[4]/
CLKX1/
CLKR1/
GP4[12]
GP0[5]
GP0[6]
AHCLKX/
AXR15/
EPWM0TZ[0]/
EMA_WEN_DQM[1]/
UART1_CTS
/
ECAP2_APWM2/
GP2[2]
GP0[10]/
GP0[7]
PRU0_R31[17]
3
4
5
Figure 3-4. Pin Map (Quad D)
Submit Documentation Feedback
Product Folder Links:
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6
7
8
CV
V
SS
V
DD
SS
CV
CV
V
DD
DD
SS
DV
CV
DD18
CV
DD
DD
DV
DV
DV
DD3318_B
DD3318_B
DD3318_B
EMA_D[15]/
EMA_D[5]/
EMA_D[3]/
GP3[7]
GP4[13]
GP4[11]
EMA_SDCKE/
EMA_D[11]/
EMA_D[7]/
PRU0_R30[4]/
GP3[3]
GP4[15]
GP2[6]/
PRU0_R31[4]
EMA_D[6]/
EMA_D[14]/
EMA_WEN_DQM[0]/
GP4[14]
GP3[6]
GP2[3]
EMA_CLK/
EMA_D[13]/
PRU0_R30[5]/
EMA_D[2]/
GP3[5]
GP2[7]/
GP4[10]
PRU0_R31[5]
EMA_D[12]/
EMA_D[10]/
EMA_D[1]/
GP3[4]
GP3[2]
GP4[9]
6
7
8
AM1808
AM1808
A
D
C
9
10
V
V
SS
SS
J
V
CV
SS
DD
H
DV
DV
DD3318_B
DD18
G
EMA_CS[4]/
DV
DD3318_B
F
GP3[13]
MMCSD0_CLK/
EMA_D[8]/
PRU1_R30[31]/
E
GP3[0]
GP4[7]
EMA_D[9]/
EMA_A_R /
W
D
GP3[1]
GP3[9]
EMA_A[19]/
EMA_D[0]/
MMCSD0_DAT[2]/
C
GP4[8]
PRU1_R30[27]/
GP4[3]
EMA_A[21]/
MMCSD0_DAT[0]/
EMA_WE/
B
PRU1_R30[29]/
GP3[11]
GP4[5]
EMA_CAS/
EMA_A[22]/
PRU0_R30[2]/
MMCSD0_CMD/
A
PRU1_R30[30]/
GP2[4]/
GP4[6]
PRU0_R31[2]
9
10
Device Overview
B
17
Advertisement
Table of Contents
