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Figure 11–53. SPI Configuration: McBSP as the Slave
Table 11–21. SPI-Mode Clock Stop Scheme
CLKSTP
CLKXP
0X
X
10
0
11
0
10
1
11
1
McBSP slave
The clock stop mode (CLKSTP) of the McBSP provides compatibility with the
SPI protocol. The McBSP supports two SPI transfer formats which are specified
by the clock stop mode field (CLKSTP) in the SPCR. The clock stop mode field
(CLKSTP) in conjunction with the CLKXP bit in the PCR allows serial clocks to
be stopped between transfers using one of four possible timing variations, as
shown in Table 11–21. Figure 11–54 and Figure 11–55 show the timing
diagrams of the two SPI transfer formats and the four timing variations.
Clock Scheme
Clock stop mode disabled. Clock enabled for non-SPI mode.
Low inactive state without delay. The McBSP transmits data on the rising edge
of CLKX and receives data on the falling edge of CLKR.
Low inactive state with delay. The McBSP transmits data one-half cycle ahead
of the rising edge of CLKX and receives data on the rising edge of CLKR.
High inactive state without delay. The McBSP transmits data on the falling
edge of CLKX and receives data on the rising edge of CLKR.
High inactive state with delay. The McBSP transmits data one-half cycle ahead
of the falling edge of CLKX and receives data on the falling edge of CLKR.
SPI compliant
master
CLKX
SCK
DX
MISO
DR
MOSI
FSX
SS
Multichannel Buffered Serial Ports
SPI Protocol: CLKSTP
11-81
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