Texas Instruments TMS320C6201 Reference Manual page 385

Tms320c6000 series peripherals

Hide thumbs Also See for TMS320C6201:

Table of Contents

11.5.4.3 Double-Rate Clock

Figure 11–45. Double-Rate Clock Example

CLK(R/X)_int

This example is the same as the ST-BUS example except for the following:

CLKSP = 0: The rising edge of CLKS generates CLKG and CLK(R/X).

CLKGDV = 1: CLKG, CLKR_int, and CLKX_int frequencies are half of the

CLKS frequency.

GSYNC = 0: CLKS drives CLKG. CLKG runs freely and is not resynchro-

nized by FSR.

FS(R/X)M = 0: Frame synchronization is externally generated. The fram-

ing pulse is wide enough to be detected.

FS(R/X)P = 0: Active (high) input frame sync signal

(R/X)DATDLY = 1: Specifies a data delay of one bit

Programmable Clock and Framing

Multichannel Buffered Serial Ports

Chapters

Table of Contents