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2.3
L3 and L4 Memory Space Mapping
The memory space system is hierarchical: L1, L2, L3, and L4.
L1 and L2 are memories in the MPU and IVA2.2 subsystems.
The chip-level interconnect, which consists of one L3 and four L4s, enables communication among all
modules and subsystems.
L3 handles many types of data transfers, including data exchange with system on-chip/external memories.
The four L4s handle transfers with peripherals, but are in four distinct power domains: the L4-Core,
L4-Wakeup, L4-Per, and L4-Emu interconnects, which are in the CORE, WKUP, PER, and EMU power
domains, respectively.
For more information about the interconnect, see
The following sections describe the register mapping of the L3 and L4 interconnects. Software configures
these registers.
2.3.1 L3 Memory Space Mapping
The L3 interconnect control registers are mapped in a 16-MB space and allow the configuration of the L3
interconnect parameters.
The L3 default settings are fully functional and enable all possible functional data paths. However, the
interconnect parameters can be changed to accommodate requirements.
Accesses to the L3 interconnect can be configured on a per-module basis using the internal L3 registers,
which are grouped into five register block types:
•
IA: Initiator agent configuration registers
•
TA: Target agent configuration registers
•
RT: Register target (global) configuration registers
•
PM: Protection mechanism (firewalls) configuration registers
•
SI: Global sideband signal configuration registers
For more information, see
This section describes all modules and features in the high-tier device. In unavailable modules and
features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
Table 2-2
describes the mapping of the L3 interconnect control registers.
Device Name
L3 RT
L3 SI
Reserved
MPU subsystem IA
IVA2.2 subsystem IA
SGX subsystem IA
SMS TA
GPMC TA
OCM RAM TA
OCM ROM TA
D2D IA
SWPU177N – December 2009 – Revised November 2010
Public Version
Chapter
9, Interconnect.
Table 2-2. L3 Control Register Mapping
Start Address
End Address
(Hex)
0x6800 0000
0x6800 03FF
0x6800 0400
0x6800 07FF
0x6800 0800
0x6800 13FF
0x6800 1400
0x6800 17FF
0x6800 1800
0x6800 1BFF
0x6800 1C00
0x6800 1FFF
0x6800 2000
0x6800 23FF
0x6800 2400
0x6800 27FF
0x6800 2800
0x6800 2BFF
0x6800 2C00
0x6800 2FFF
0x6800 3000
0x6800 33FF
Copyright © 2009–2010, Texas Instruments Incorporated
Chapter
9, Interconnect.
Size (KB)
(Hex)
1
1
3
1
1
1
1
1
1
1
1
L3 and L4 Memory Space Mapping
Description
L3 configuration registers
Sideband signal configuration
Reserved
MPU subsystem instruction port agent
configuration
IVA2.2 subsystem initiator port agent
configuration
SGX subsystem initiator port agent
configuration
SMS target port agent configuration
GPMC target port agent configuration
OCM RAM target port agent
configuration
OCM ROM target port agent
configuration
Die-to-die (D2D) initiator port agent
configuration
Memory Mapping
209
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