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EMIF: The EMIF supports a glueless interface to several external devices, in-
cluding:
Synchronous burst SRAM (SBSRAM)
Synchronous DRAM (SDRAM)
Asynchronous devices, including SRAM, ROM, and FIFOs
An external shared-memory device
Boot Configuration: The TMS320C62x and TMS320C67x provide a variety
of boot configurations that determine what actions the DSP performs after de-
vice reset to prepare for initialization. These include loading in code from an
external ROM space on the EMIF and loading code through the HPI/expan-
sion bus from an external host.
McBSP: The multichannel buffered serial port (McBSP) is based on the stan-
dard serial port interface found on the TMS320C2000 and 'C5000 platform de-
vices. In addition, the port can buffer serial samples in memory automatically
with the aid of the DMA/EDMA controller. It also has multichannel capability
compatible with the T1, E1, SCSA, and MVIP networking standards. Like its
predecessors, it provides:
Full-duplex communication
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips
(AICs), and other serially connected A/D and D/A devices
In addition, the McBSP has the following capabilities:
Direct interface to:
J
T1/E1 framers
t
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ST-BUS
compliant devices
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IOM-2 compliant devices
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AC97 compliant devices
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IIS compliant devices
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SPI devices
Multichannel transmission and reception of up to 128 channels
A wider selection of data sizes including 8-, 12-, 16-, 20-, 24-, and 32-bits
µ-law and A-law companding
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Overview of TMS320C6000 Peripherals
Introduction
1-11
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