Texas Instruments TMS320C6201 Reference Manual page 382

Programmable Clock and Framing
Table 11–18. Transmit Frame Synchronization Selection
FSXM FSGM
in PCR in SRGR
0 X
1 1
1 0
11.5.3.4 Frame Detection for Initialization
11-64
Source of Transmit Frame
Synchronization
External frame sync input on the FSX
pin. This is inverted by FSXP before be-
ing used as FSX_int.
Sample rate generator frame sync signal
(FSG) drives FSX_int. FRST = 1
A DXR-to-XSR copy activates transmit
frame sync signal.
To facilitate detection of frame synchronization, the receive and transmit CPU
interrupts (RINT and XINT) can be programmed to detect frame synchroniza-
tion by setting RINTM = XINTM = 10b in the SPCR. Unlike other types of serial
port interrupts, this one can operate while the associated portion of the serial
port is in reset (for example, RINT can be activated while the receiver is in re-
set). In that case, the FS(R/X)M and FS(R/X)P still select the appropriate
source and polarity of frame synchronization. Thus, even when the serial port
is in reset, these signals are synchronized to the CPU clock and then sent to
the CPU in the form of RINT and XINT at the point at which they feed the re-
ceive and transmit portions of the serial port. A new frame synchronization
pulse can be detected, after which the CPU can safely take the serial port out
of reset.
FSX Pin Function
Input
Output. FSG is inverted by FSXP be-
fore being driven out on FSX.
Output. 1-bit-clock-wide signal inverted
as determined by FSXP before being
driven out on FSX.