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2.6.4
Data Alignment
2.6.5
Dual CPU Accesses to Internal Memory
The following data alignment restrictions apply:
Doublewords: ('C6701 only) Doublewords are aligned on even 8-byte (dou-
bleword) boundaries, and always start at a byte address where the three LSBs
are 0. Doublewords are used only on loads triggered by the LDDW instruction.
Store operations do not use doublewords.
Words: Words are aligned on even 4-byte (word) boundaries, and always start
at a byte address where the two LSBs are 0. A word access requires two adja-
cent 16-bit-wide banks.
Halfwords: Halfwords are aligned on even 2-byte (halfword) boundaries, and
always start at byte addresses where the LSB is 0. Halfword accesses require
the entire 16-bit-wide bank.
Bytes: There are no alignment restrictions on byte accesses.
Both the CPU and DMA can read and write 8-bit bytes, 16-bit halfwords, and
32-bit words. The data memory controller performs arbitration individually for
each 16-bit bank. Although arbitration is performed on 16-bit-wide banks, the
banks have byte enables to support byte-wide accesses. However, a byte ac-
cess prevents the entire 16 bits containing the byte from simultaneously being
used by another access.
As long as multiple requesters access data in separate banks, all accesses are
performed simultaneously with no penalty. Also, when two memory accesses
involve separate 32K byte memory blocks, there are no memory conflicts, re-
gardless of the address. For multiple data accesses within the same block, the
memory organization also allows simultaneous multiple memory accesses as
long as they involve different banks. In one CPU cycle, two simultaneous ac-
cesses to two different internal memory banks occur without wait states. Two
simultaneous accesses to the same internal memory bank stall the entire CPU
pipeline for one CPU clock, providing two accesses in two CPU clocks. These
rules apply regardless of whether the accesses are loads or stores.
TMS320C6201/C6701 Program and Data Memory
Internal Data Memory Organization
2-15
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