Texas Instruments TMS320C6201 Reference Manual page 196

Overview
8.1 Overview
Figure 8–1. Expansion Bus Block Diagram
DMA controller
Expansion bus host channel
8-2
The expansion bus is a 32-bit wide bus that supports interfaces to a variety of
asynchronous peripherals, asynchronous or synchronous FIFOs, PCI bridge
chips, and other external masters.
The expansion bus offers a flexible bus arbitration scheme, implemented with
two signals, XHOLD and XHOLDA. The expansion bus can operate with the
Internal arbiter enabled, in which case any external hosts must request the bus
from the DSP. For increased flexibility, the internal arbiter can be disabled, and
the DSP requests the bus from an external arbiter.
The expansion bus has two major sub blocks—the I/O port and host port inter-
face. A block diagram of the expansion bus is shown in Figure 8–1.
Expansion bus
XCLKIN
XFCLK
XD[31:0]
XCE[3:0]
Shared signals
XBE[3:0]/XA[5:2]
XWE/XWAIT
I/O Port:
XOE
asynchronous
XRE peripheral/
FIFO interface
XCS
XAS
XCNTL
XW/R
Host port interface
XRDY
XBLAST
XBOFF
XHOLD
Bus arbitration signals
XHOLDA