Texas Instruments TMS320C6201 Reference Manual page 194

7.5 Memory Access Through the HPI During Reset
Host Access Sequences / Memory Access Through the HPI During Reset
Writes to and reads from HPIA: In Table 7–7, the portion of HPIA accesses
selected by HHWIL and HWOB is updated automatically after each half-
word access. Thus, to change either the upper or the lower 16 bits of HPIA,
the host must select the half to modify through a combination of the HHWIL
and HWOB bits. The host can also choose to read only half of HPIA.
HPID read accesses: Read accesses are actually triggered by the first
halfword access (HHWIL low). Thus, if on reads the host is interested only
in the first halfword (the least or most significant halfword, as selected by
HWOB), the host does not need to request the second address. However,
prefetching does not occur unless the second halfword is also read. A sub-
sequent read of the first halfword (HHWIL low) or a write of a new value
to HPIA overrides any previous prefetch request. On the other hand, a
read of just the second halfword (HHWIL high) is not allowed and results
in undefined operation.
Write accesses: Write accesses are triggered by the second halfword access
(HHWIL word high). Thus, if the host desires to change only the portion of
HPID selected by HHWIL high (and the associated byte enables) during con-
secutive write accesses, only a single cycle is needed. This technique's pri-
mary use is for memory fills: the host writes both halfwords of the first write
access with HBE[1:0] = 00. On subsequent write accesses, the host writes
the same value to the portion of HPID selected by HHWIL as the first write
access did. In this case, the host performs autoincrementing writes
(HCNTL[1:0] = 10) on all write accesses.
During reset, when HCS is active low, HRDY is inactive high, and when HCS is
inactive, HRDY is active. The HPI cannot be used while the chip is in reset. How-
ever, certain boot modes can allow the host to write to the CPU's memory space
(including configuring EMIF configuration registers to define external memory be-
fore accessing it). Although the device is not in reset during these boot modes,
the CPU itself is in reset until the boot completes. See Chapter 10, Boot Configu-
ration, Reset, and Memory Maps , for more details.
Memory Access Through the HPI During Reset
Host-Port Interface 7-27