Texas Instruments TMS320C6201 Reference Manual page 372

Programmable Clock and Framing
11.5.1 Sample Rate Generator Clocking and Framing
Figure 11–38. Sample Rate Generator
internal clock source †
CLKS
CLKSP
† 'C6201/C6202/C6701 uses CPU clock as the internal clock source to the sample rate generator.
'C6211/C6711 uses CPU/2 clock as the internal clock source to the sample rate generator.
11-54
The sample rate generator is composed of a 3-stage clock divider that provides
a programmable data clock (CLKG) and framing signal (FSG), as shown in
Figure 11–38. CLKG and FSG are McBSP internal signals that can be pro-
grammed to drive receive and/or transmit clocking, CLK(R/X), and framing,
FS(R/X). The sample rate generator can be programmed to be driven by an inter-
nal clock source or an internal clock derived from an external clock source. The
three stages of the sample rate generator circuit compute:
Clock divide-down (CLKGDV): The number of input clocks per data bit
clock
Frame period (FPER): The frame period in data bit clocks
Frame width (FWID): The width of an active frame pulse in data bit clocks
In addition, a frame pulse detection and clock synchronization module allows
synchronization of the clock divide-down with an incoming frame pulse. The
operation of the sample rate generator during device reset is described in
section 11.3.1.
CLKSRG
1
0
CLKSM
GSYNC
FSR
CLKGDV FPER
Frame pulse
detection
and clock
synchronization
FWID
Frame FSG
pulse
CLKG