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11.5.2.7 Transmit Clock Selection: CLKXM
Table 11–16. Transmit Clock Selection
CLKXM
Source of Transmit Clock
in PCR
0
The external clock drives the CLKX input pin.
CLKX is inverted as determined by CLKXP
before being used.
1
The sample rate generator clock, CLKG,
drives the transmit clock
11.5.3 Frame Sync Signal Generation
Table 11–16 shows how the CLKXM bit in the PCR selects the transmit clock
and whether the CLKX pin is an input or output.
Data frame synchronization is independently programmable for the receiver and
the transmitter for all data delay values. When set to 1 the FRST bit in the SPCR
activates the frame generation logic to generate frame sync signals, provided that
FSGM = 1 in SRGR. The frame sync programming options are:
A frame pulse with a programmable period between sync pulses and a pro-
grammable active width specified in the sample rate generator register
(SRGR).
The transmitter can trigger its own frame sync signal that is generated by
a DXR-to-XSR copy. This causes a frame sync to occur on every DXR-to-
XSR copy. The data delays can be programmed as required. However,
maximum packet frequency cannot be achieved in this method for data
delays of 1 and 2.
Both the receiver and transmitter can independently select an external frame
synchronization on the FSR and FSX pins, respectively.
Programmable Clock and Framing
CLKX Function
Input
Output. CLKG is inverted as determined by
CLKXP before being driven out on CLKX.
Multichannel Buffered Serial Ports
11-61
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