Texas Instruments TMS320C6201 Reference Manual page 460

Index
asynchronous mode 8-5
asynchronous or synchronous FIFOs 8-2
asynchronous peripheral FIFO interface 8-2
asynchronous peripherals 8-2
asynchronous read timing example, figure 9-55
auto–initialization feature 6-16
autoincrement 7-22
auxiliary port 8-3
B
B register file 8-4
background refreshes 9-24
bank collision 4-15
base address register 4-8
big endian (BE) 7-8
bit descriptions, HPI control register 7-17
bit ordering 11-52
bits, HOLD and HOLDA 9-28
block, definition 6-5
block diagram
EMIF 9-4
expansion bus 8-2
externalmemory interface in the
TMS320C6201/C6701 9-3
host port interface 7-4
internal memory 4-3
McBSP 11-3
timers 12-3
TMS320C6201/6202/6701 1-9
TMS320C6201/C6701 7-2
TMS320C6201/C6701 program memory
controller 2-2
TMS320C6202 data memory controller 3-7
TMS320C6202 program memory controller 3-3
TMS320C6211 1-10, 4-2
block transfer 5-2
block transfers 5-13, 6-5
Boot configuration 1-8
boot configuration 1-11
boot mode pins 10-3
boot process 10-8
HPI boot process 10-9
memory at reset address 10-8
memory map 10-5
overview 10-2
ROM boot process 10-8
Index-2
TMS320C6211 summary 10-5
boot configuration control via expansion bus 8-49
bootload
note on program memory 2-6
TMS320C6202 3-6
bootload operation 3-6
BSP serial port control extension register (SPCE)
CLKP bit 11-13
FSP bit 11-12
buffered signals, JTAG 15-9
buffering 15-8
bus arbitration scheme 8-2
bus arbitration signals 8-2
bus connections between the CPU, internal
memories, and the enhanced DMA 4-2
bus data 8-7
bus devices 15-3
bus protocol 15-3
buses
data 7-7
external 9-60
HPI access 7-12
byte enable pins 7-8
C
cable, target system to emulator 15-1 to 15-24
cable pod 15-4
cache 1-6, 2-1
architecture 2-4
bypass 2-4
fetch packet figure 2-5
flush 2-5
logical mapping of address 2-5
miss 2-3, 2-5
usage of CPU address 2-5
cache , flush 2-5
Cache Configuration Register (CCFG) 4-15
cache configuration register (CCFG) 4-7, 4-12
Cache Configuration Register Field Description,
table 4-13
cache data 4-7, 4-11
cache data request 4-17
cache, freeze 2-3
cache hit 4-6
cache miss 4-6, 4-10
cache operation 3-5