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L1P Description
4.3 L1P Description
Figure 4–4. L1P Address Allocation
31
Tag
Table 4–4. Level 1 Program Cache Mode Settings
4-6
The L1P is organized as a 64 line direct mapped cache with a 64 byte (2 fetch
packet) line size. The L1P data request size is one line, thus the six least
significant bits of a requested address are ignored. The next six bits of the ad-
dress are used to reference the set within the cache that the addressed data
maps to. The remaining bits of the address are used as a unique tag for the
requested data. Figure 4–4 illustrates how a 32 bit address is allocated to pro-
vide the set index and tag data for the L1P.
12
11
A cache hit returns data to the CPU in a single cycle.
TMS320C6201, the L1P only operates as a cache and cannot be memory
mapped. The L1P does not support freeze or bypass modes. The only values
allowed for the program cache control (PCC) field in the CPU control and sta-
tus register (CSR) are 000b and 010b. All other values for PCC are reserved,
as shown in Table 4–4.
Cache Mode
PCC value
Cache enable
Cache enable
Any initial program fetch of an address causes a cache miss to occur. The data
is requested from the L2 and stored in the internal cache memory. Any subse-
quent read from a cached address causes a cache hit and that data is loaded
from the L1P memory. Figure 4–5 illustrates the organization of a direct
mapped cache.
6
Set
Description
010b
Direct mapped cache
000b
Direct mapped cache
other
Reserved
5
0
Offset
Unlike the
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