Texas Instruments TMS320C6201 Reference Manual page 433

Table 14–4. Description of TMS320C6202 Power-Down Control Fields
Field Description
PDDMA
Enable/disable internal DMA clock
PDDMA=0:
PDDMA=1:
PDEMIF
Enable/disable internal EMIF clock
PDEMIF=0:
PDEMIF=1:
PDMCSP0
Enable/disable internal McBSP0 clock
PDMCSP0=0: Internal McBSP0 clock allowed to clock.
PDMCSP0=1: Internal McBSP0 clock disabled. McBSP0 is not functional.
PDMCSP1
Enable/disable internal McBSP1 clock
PDMCSP1=0: internal McBSP1 clock allowed to clock.
PDMCSP1=1: internal McBSP1 clock disabled, McBSP1 is not functional.
PDMCSP2
Enable/disable internal McBSP2 clock
PDMCSP2=0: internal McBSP2 clock allowed to clock
PDMCSP2=1: internal McBSP2 clock disabled, McBSP2 is not functional
Table 14–4 lists and describes the fields in the TMS320C6202 peripheral
power-down memory-mapped register.
internal DMA clock allowed to clock
internal DMA clock disabled. DMA is not functional
internal EMIF clock allowed to clock
Internal EMIF clock disabled. EMIF is not functional. The HOLD
condition which exists at power down will remain active and
external clocks continue to clock.
Additional Power-Saving Modes for the TMS320C6202
Power-Down Logic
Section
14.3
14.3
14.3
14.3
14.3
14-7