Texas Instruments TMS320C6201 Reference Manual page 472

Index
program access/cache controller 8-4
program address 4-3
program and data busses 4-1
program cache control (PCC) 2-3, 4-6
program cache control (PCC) field 4-6
program cache mode settings, L1P 4-6
program fetch 2-3, 3-3
program memory 2-1, 3-2
internal 1-6, 2-3
internal mode summary 2-4
note on bootload 2-6
program memory , DMA controller access 2-6
program memory controller 2-2, 9-5
program memory controller (PMEMC) 3-2
program RAM address mapping 3-5
programmable clock and framing
double-rate clock 11-67
double-rate ST-BUS clock 11-65
examples 11-65
single-rate ST-BUS clock 11-66
programmable parameters 9-53
Programmable Priority Levels for Data Requests,
table 6-36
protocol, bus 15-3
pullup and pulldown resistors on XD 8-50
pulse generation 12-9
Q
quick DMA (QDMA) 6-38
performance 6-40
registers 6-38
R
R/WSYNC event (FS=0) 6-20
R/WSYNC Non–2D Transfer
RAM 3-7
RAM address mapping 3-5
RAM–based architecture 6-9
read access with autoincrement 7-22
read FIFO interface 8-17
read hold and write hold fields 9-14
read hold bit fields 9-13
read strobe 9-12
Index-14
6-20
Read/Write FIFO Interface With Glue, figure 8-16
read/write synchronization 6-19
Read/Write Synchronized 2–D Transfer
(No Frame Sync), figure 6-23
ready signals 8-27
ready status 11-21
)receive buffer register (RBR 11-4
receive control register 11-14
receive data clocking, figure 11-25
receive data justification 11-49
receive event 6-18
receive interrupt (RINT) 11-22
receive operation 11-34
receive shift register (RSR 11-4
reception, data 11-18
recovery phase (Tr) 8-36
refresh, SDRAM 9-26
register file 8-4
register–based architecture 6-9
registers
'C6211 EMIF CE space control 9-12
base address 4-8
boundary conditions 12-11
cache configuration 4-5
cache configuration
channel chain enable 6-6
channel chain enable register 6-35
channel interrupt enable
channel interrupt pending 6-6, 6-32
control and status 2-3, 4-6
CSR 14-3
data transmit register (DXR) 11-4
destination address 5-22
DMA 5-5
DMA channel control 5-8
DMA channel primary control 5-23
DMA channel reload 5-14
DMA channel secondary control 5-10
DMA control by address 5-6
DMA control by name 5-7
DMA global count reload 5-16
DMA global index 5-23
EDMA control 6-6
EMIF 9-9
EMIF CE space control 9-12
EMIF global control 9-9
EMIF global control , field descriptions 9-10
EMIF SDRAM control 9-15
4-7, 4-15
6-6, 6-32