Texas Instruments TMS320C6201 Reference Manual page 162

Resource Arbitration and Priority Processing
6.14 Resource Arbitration and Priority Processing
Table 6–10. Programmable Priority Levels for Data Requests
6-36
The 16 EDMA channels can have programmable priority in the two lower
levels. The PRI bit in options specifies the two priority levels: level1 (high prior-
ity, PRI = 001b) and level 2 (low priority, PRI = 010b). The highest priority avail-
able in the system is level 0 or the urgent priority, which is dedicated to L2 re-
quests. L2 requests comprise of data and program requests from the CPU, L1
and L2 controllers. The EDMA controller and the host port interface (HPI) can
submit requests with either of the two lower priority levels.
PRI(31:29) Priority Level
000b Level0; urgent priority
001b Level1; high priority
010b Level2; low priority
011b – 111b Reserved
The user should take care in not over-burdening the system by not submitting
all requests in high priority. Oversubscribing requests in one priority level can
cause EDMA stalls. This can be alleviated by balanced bandwidth distribution
in the two levels of priority.
The requesters in the 'C6211/C6711 device include the L2 controller, the
EDMA, and the HPI. The HPI and L2 controller have direct ties to the address
generation hardware, so no EDMA parameter RAM is required for access re-
quests from these sources. The resources for the various requesters include
the L2 SRAM space, the various peripheral registers, and the external memory
space managed by the EMIF. Due to the number of requesters and resources,
there are situations where one or more requesters contend for the same re-
source. An example would be the EDMA and CPU requesting data from the
same bank in L2 SRAM. The L2 controller resolves this contention by examin-
ing the user-specified 'P' bit in L2CFG register (see Section 4.5 in
TMS320C6211/C6711 Internal Memory). The L2 controller prioritizes and seri-
alizes the requests from these modules. If P is equal to 1, the EDMA request
gets priority over the CPU.
Requesters
L2 controller
EDMA and/or HPI
EDMA and/or HPI
Reserved