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Overview
14.1 Overview
14-2
Most of the operating power of CMOS logic is dissipated during circuit switching
from one logic state to another. By preventing some or all of chip's logic from
switching, significant power savings can be realized without losing any data or
operational context. PD1, PD2, and PD3 are three power-down modes avail-
able to perform this function. Power-down mode PD1 blocks the internal clock
inputs at the boundary of the CPU, preventing most of its logic from switching.
PD1 effectively shuts down the CPU. Additional power savings are accom-
plished in power-down mode PD2, where the entire on-chip clock structure
(including multiple buffers) is "halted" at the output of the PLL (see Figure 14–1).
PD3 is like PD2 but also disconnects the external clock source (CLKIN) from
reaching the PLL. Wake-up from PD3 takes longer then wake-up from PD2 be-
cause the PLL needs to be re-locked, just as it does following power-up.
On the 'C6201/C6202/C6701, both the PD2 and PD3 signals also assert the
PD pin for external recognition of these two power-down modes. Although the
'C6211/C6711 has power-down modes identical to the other devices, there is
no PD pin driven externally. In addition to power-down modes described in this
chapter, the IDLE instruction provides lower CPU power consumption by exe-
cuting continuous NOPs. The IDLE instruction terminates only upon servicing
an interrupt.
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