Texas Instruments TMS320C6201 Reference Manual page 66

Two-Level Internal Memory
The TMS320C6211/C6711 provides a two level memory architecture for the
internal program and data busses. The first level memory for both the internal
program and data bus is a 4K byte cache, designated L1P for the program
cache and L1D for the data cache. The second level memory is a 64K byte
memory block that is shared by both the program and data memory buses,
designated L2.
Topic
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Internal Memory Control Registers
4.3 L1P Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 L1D Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 L2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320C6211/C6711
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Chapter 4
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