Texas Instruments TMS320C6201 Reference Manual page 366

Data Transmission and Reception
Figure 11–32. Unexpected Transmit Frame Synchronization Pulse
CLKX
FSX
DX
A1 A0
XRDY
DXR-to-XSR copy (B)
XSYNCERR
11-48
Case 3: Unexpected transmit frame synchronization with XFIG = 0. The
case for frame synchronization with XFIG = 0 at maximum packet frequen-
cy is shown in Figure 11–20. Figure 11–32 shows the case for normal op-
eration of the serial port with interpacket intervals. In both cases, XSYN-
CERR in the SPCR is set. XSYNCERR can be cleared only by transmitter
reset or by writing a 0 to this bit in the SPCR. If XINTM = 11b in the SPCR,
XSYNCERR drives the receive interrupt (XINT) to the CPU.
Note:
The XSYNCERR bit in the SPCR is a read/write bit, so writing a 1 to it sets the
error condition. Typically, writing a 0 is expected.
B7 B6 B5
Write of DXR (C)
Unexpected frame synchronization
B4 B7 B6 B5 B4 B3 B2 B1 B0
DXR-to-XSR (C) Write of DXR (D)