Texas Instruments TMS320C6201 Reference Manual page 271

The 'C6201/C6202/C6701 EMIF SDRAM controller prioritizes SDRAM refresh
requests with other data access requests posted to it from the EMIF request-
ers. The following rules apply:
A counter value of 11 invalidates the page information register, forcing the
controller to close the current SDRAM page. The value 11 indicates an ur-
gent refresh condition. Thus, following the DCAB command, the EMIF
SDRAM controller performs three REFR commands, thereby decrement-
ing the counter to 00 before proceeding with the remainder of the current
access. If SDRAM is present in multiple CE spaces, the DCAB-refresh
sequence occurs in all spaces containing SDRAM.
During idle times on the SDRAM interface(s), if no request is pending from
the EMIF, the SDRAM interface performs REFR commands as long as the
counter value is nonzero. This feature reduces the likelihood of having to
perform urgent refreshes during actual SDRAM accesses. If SDRAM is
present in multiple CE spaces, this refresh occurs only if all interfaces are
idle with invalid page information.
Unlike the 'C6201/C6202/C6701 EMIF, the 'C6211/C6711 REFR requests are
considered high priority, and no distinction exists between urgent and trickle
refresh. Transfers in progress are allowed to complete. The 'C6211/C6711
SDRAM refresh period has an extra bitfield, XRFR, which controls the number
of refreshes performed when the counter reaches zero. This feature allows the
XRFR field to be set to perform up to four refreshes when the refresh counter
expires.
SDRAM Interface
External Memory Interface 9-27