Texas Instruments TMS320C6201 Reference Manual page 474

Index
suggested timings 15-21
scan paths, TBC emulation connections for JTAG
scan paths 15-23
scratch pad RAM 6-9
SCSA standards 1-11
SD_INT 6-18
SDA10 pin 9-6
SDRAM
address shift 9-32
control pins 9-23
deactivation 9-35
EMIF timing register 9-17
initialization 9-25, 9-26
interface 9-20
mode register set 9-28
page boundaries 9-25
read 9-37
timing requirements 9-34
write 9-39
SDRAM commands 9-20
second level memory 4-1
selection of clock sources 12-8
send synchronization events to the DMA 12-2
sequential host accesses 7-22
serial port, reset 11-18
serial port configuration 11-7
serial port control register, figure 11-7
serial port exception conditions 11-41
serial port initialization 11-20
serial ports, time-division multiplexed (TDM) 11-78
set index 4-9
set index and tag data 4-6
shared signals 8-2
sign extension 11-49
signal descriptions, 14-pin header 15-2
signal timing interrupt 13-5
signals
acknowledge 8-26
address strobe 8-27
address/data bus 8-27
ARDY 9-56
asynchronous 8-5
buffered 15-9
buffering for emulator connections 15-8 to
15-11
burst last 8-27
Index-16
bus back–off 8-27
byte enable 8-27, 8-41
chip select 8-26, 8-41
clock input 8-26
control 8-27, 8-41
data 8-14
data bus 8-41
description, 14-pin header 15-2
EMIF signal descriptions 9-7
expansion bus 8-5
FIFO clock output 8-14
FIFO output enable 8-14
FIFO read enable 8-14
FIFO read enable/write enable/chip select 8-14
FIFO write enable 8-14
frame sync 11-23
handshake 9-60
hold request 8-26
host port interface 7-7
McBSP 11-3
McBSP interface 11-5
read/write 8-27, 8-41
ready out/ready in 8-27
receive interrupt (RINT) 11-22
SDRAM 9-23
synchronous 8-5
timing 15-5
transmit interrupt (XINT) 11-22
XCNTL 8-7
XHOLD and XHOLDA 8-44
signals
expansion bus address 8-14
ready out 8-41
single frame transfer 8-20, 8-21
single phase fram of four 8–bit elements,
figure 11-29
single phase frame of one 32–bit element 11-29
single-rate ST-BUS clock 11-66
slave address 8-7
slave devices 15-3
slave mode 8-3
snoop address 4-3
software handshaking 7-17
source or destination address update 6-29
source update mode (SUM) 6-30
source/destination address 6-14
sources of interrupts 13-2
space control register 8-6, 9-12
space control registers 8-6