Texas Instruments TMS320C6201 Reference Manual page 304

Hold Interface
9.7 Hold Interface
9-60
The EMIF responds to hold requests for the external bus. The hold handshake
allows an external device and the EMIF to share the external bus. The hand-
shake mechanism uses two signals:
HOLD: hold request input. HOLD is synchronized internally to the CPU
clock. This synchronization allows an asynchronous input while avoiding
metastability. The external device drives this pin low to request bus ac-
cess. HOLD is the highest priority request that the EMIF can receive dur-
ing active operation. When the hold is requested, the EMIF stops driving
the bus at the earliest possible moment, which may entail completion of
the current accesses, device deactivation, and SDRAM bank deactiva-
tion. The external device must continue to drive HOLD low for as long as
it wants to drive the bus. If any memory spaces are configured for SDRAM,
these memory spaces are deactivated and refreshed after HOLD is re-
leased by the external master.
HOLDA: Hold acknowledge output. The EMIF asserts this signal active
after it has placed its signal outputs in the high-impedance state. The
external device can then drive the bus as required. The EMIF places all
outputs in the high-impedance state with the exception of the clock out-
puts: CLKOUT1, CLKOUT2, SDCLK, and/or SSCLK, depending on the
device. If any memory spaces are configured for SDRAM, these memory
spaces are deactivated and refreshed before HOLDA is asserted to the
external master.
BUSREQ. Bus request output ('C6211/C6711 only). The EMIF asserts this
signal active when any request is either pending to the EMIF or is in pro-
gress. The BUSREQ signal is driven without regard to the state of the
HOLD/HOLDA signals or the type of access pending. This signal can be
used by an external master to release control of the bus if desired and may
be ignored in some systems.
Note:
There is no mechanism to ensure that the external device does not attempt
to drive the bus indefinitely. You should be aware of system-level issues,
such as refresh, that you may need to perform.
During host requests, the refresh counters within the EMIF continue to log re-
fresh requests; however, no refresh cycles can be performed until bus control
is again granted to the EMIF when the HOLD input returns to the inactive level.
You can prevent an external hold by setting the NOHOLD bit in the EMIF global
control register.