Texas Instruments TMS320C6201 Reference Manual page 463

direct memory access (DMA) controller 1-6, 1-7,
5-2
direct memory access (EDMA) 6-2
direct memory access channels 5-1
direct memory access controller 2-1
direct–mapped cache 3-2
DMA. See direct memory access
DMA auxiliary channel 7-3, 7-19
DMA bus controller 3-3, 3-7
DMA channel control register 5-8
DMA channel primary control register 5-23
figure 5-8
DMA channel secondary control registers,
figure 5-10
DMA channel transfer counter register, figure 5-16
DMA controller 1-10, 9-2, 9-5, 11-18
access to program memory 2-6
DMA controller interconnect to
TMS320C6201/C6701 memory mapped
modules, figure 5-4
DMA global count reload register used as a transfer
counter reload, figure 5-16
DMA global index register 5-23
DMA interrupt mapping 6-33
double-rate clock 11-67
double-rate ST-BUS clock 11-65
DSPINT 6-18
dual–phase frame example 11-26
DUM/SUM 6-14
DuPont connector 15-3
E
E1 standards 1-11
EDMA
performance 6-37
QDMA 6-38
transfer parameters 6-13
EDMA Channel Association with Sync Events,
table 6-18
EDMA Channel Options Field Description,
table 6-13
EDMA channel transfer 6-34
EDMA channels 6-34
EDMA control registers, table 6-6
EDMA Controller, figure 6-3
EDMA controller 1-10, 6-6, 6-8, 6-25, 6-28, 6-32,
6-34, 7-3
TMS320C6211 13-4
EDMA DST Address Parameter Updates,
table 6-31
EDMA Element and Frame/Line Count Updates,
table 6-28
EDMA interrupt generation 6-32
EDMA interrupt servicing by the CPU 6-34
EDMA parameter RAM 6-16, 6-18, 6-28
EDMA Parameter RAM Contents, table 6-10
EDMA SRC Address Parameter Updates,
table 6-30
EDMA stalls 6-36, 6-37
EDMA terminology 6-5
EDMA transfer 6-7
initiating 6-17
EDMA transfers, synchronization of 6-17
EDMA transfers, linking 6-25
EDMA_TCC10 6-18
EDMA_TCC11 6-18
EDMA_TCC8 6-18
EDMA_TCC9 6-18
effects of a power down 14-4
element index (EIX) 6-12
element and frame/line count updates 6-28
Element Count 6-15
element count 5-16, 6-25
element count reload 6-12
element count (EC) 6-20, 6-28
element count reload 6-15, 6-28
element index 8-10
element index (EIX 6-21
element index (EIX) 6-20, 6-28
element length 11-28
Element size 6-14
element size 6-27
element transfer 5-2, 6-5, 6-21
element transfers 6-37
Element/(Frame/Line) Index 6-15
EMA transfer parameter entry 6-12
EMIF global control register diagram, figure 9-9
EMIF to 16–bit ROM interface, figure 9-51
EMIF to 8–bit ROM interface, figure 9-51
Index
Index-5