Texas Instruments TMS320C6201 Reference Manual page 467

G
general–purpose registers 1-5
general–purpose timers 1-12
generate pulses 12-2
global control register 8-8
global control register diagram 9-9
Glue–Less Read FIFO Interface, figure 8-17
Glue–Less Write FIFO Interface, figure 8-15
glueless interface 1-11, 9-2
H
hardware reset 9-8
header
14-pin 15-2
dimensions, 14-pin 15-2
history of the TMS320 DSPs 1-2
hold disable 8-8
hold state 8-8
host access 7-19
host device 1-10
host port interface 1-9, 8-2
bootload mode 2-6
host port interface (HPI) 4-2, 6-36
host port interface data write access 7-8
host–port interface (HPI) 1-8
host-port interface (HPI)
access control selection 7-7
access sequences 7-19
block diagram 7-4
bus accesses 7-12
byte enables 7-9
control register 7-16
CPU interrupt 7-18
data bus 7-7
halfword identification select 7-8
initialization 7-19
interrupt by CPU 7-18
memory access during reset 7-27
overview 7-2
read with autoincrement 7-22
read without autoincrement 7-20
interrupt to host 7-12
read/write select 7-10
ready pin 7-10
registers 7-16
signal descriptions 7-7
software handshaking 7-17
strobes 7-10
write with autoincrement 7-25
write without autoincrement 7-23
HPI 1-10
HPI Block Diagram of TMS320C6211, figure 7-5
HPI bootload 3-6
HPI control register (HPIC) 7-5
I
I/O port 8-2
I/O port operation 8-10
Idle modes 10-1, 13-2
idle modes 14-1
IEEE 1149.1 specification, bus slave device
rules 15-3
ignore frame synchronization 11-36
in–circuit emulation 4-2, 8-4
inactive cycles 8-10
index value 5-22
initialization, SDRAM 9-25
initiate data transfer 6-17
initiating an EDMA transfer 6-17
instruction decode 1-9
instruction fetch 1-9, 8-4
instruction fetch, dispatch, and decode 4-2
interface
asynchronous 9-5
EMIF to 16–bit ROM 9-51
EMIF to 8–bit ROM 9-51
EMIF to SRAM 9-50
glueless 9-2
read FIFO 8-17
synchronous 9-5
TMS320C6202 external memory 9-5
write 8-15
interface chips 8-1
interfaces, L2 4-15
internal arbiter 8-2
internal bus arbiter disabled 8-45
internal bus arbiter enabled 8-44
internal cache memory 4-10
Internal configuration bus timer 0 registers 10-7
internal data movement 11-4
Index
Index-9