Glueless Write Fifo Interface - Texas Instruments TMS320C6201 Reference Manual

8.4.2.1 Write Interface
Figure 8–7. Glueless Write FIFO Interface
During write accesses to a memory space configured for read/write FIFO
mode, the XCE signal and XWE signal are both active for a single rising edge
of XFCLK. So, depending on the specific system environment, the write
interface can be accomplished either with glue or without glue.
The glueless interface can be used if only a single write FIFO is used in a given
XCE space (see Figure 8–7), since the XCE signal is used as the write enable
signal. If this is true, the XCE signal is tied directly to the write enable input of
the FIFO. If a read FIFO is also used in the same XCE space, glue must be
used, since the XCE signal also goes low for reads from the read FIFO.
Figure 8–8 shows an interface to a read FIFO and a write FIFO in the same
XCE space. For this example, the XCE signal is used to gate the appropriate
read/write strobes to the FIFOs. The FIFO write timing diagram for this
interface is shown in Figure 8–9.
Several FIFOs can be accessed in a single XCE space if address decode logic
is used to access each FIFO separately.
XFCLK
XCEn
Expansion
XWE
bus
XRE
EXT_INTx
XD[31:0]
Expansion Bus I/O Port Operation
WCLK RCLK
WEN REN
OE
Synchronous
FIFO
EF
FF
HF
D[31:0] Q[31:0]
Expansion Bus 8-15