Texas Instruments TMS320C6201 Reference Manual page 80

4.5.1 L2 Interfaces
4.5.2
L2 Operation
The L2 Controller services requests from three different requestors – the L1P,
the L1D, and the Enhanced DMA. Since the L1P only sends read requests,
a single 256 bit wide data bus transfers data from the L2 to the L1P. The L1D
to L2 interface consists of a 128 bit read bus from the L2 to the L1D and a 128
bit write bus from the L1D to the L2. The L2 transfers data to and from the
EDMA through a 64 bit read and a 64 bit write bus.
Each L1D access to the L2 memories takes two cycles. Since the line size of
L1D cache is twice the width of the bus between the cache and the L2, a miss
to the L2 requires two accesses. Therefore, a miss from L1D to the L2 takes
four cycles to complete if the data is available in the L2. A miss from the L1P
to the L2 completes in five cycles.
The L2 memories are organized as four 64 bit wide banks. Two accesses can
be serviced at the same time if the two accesses do not use the same bank.
Since the L1P data bus is 256 bits wide, any L1P request that occurs at the
same time as an L1D or EDMA request will cause a bank collision and there-
fore a stall. Concurrent accesses between the L1D and EDMA busses to differ-
ent banks can be serviced without stalling.
The priority bit (P) in the Cache Configuration Register (CCFG) determines the
priority when a bank collision occurs between requestors. If the P bit is set to
0, CPU accesses (L1P and L1D) are given priority over an EDMA request.
Thus, any pending CPU request will complete before the EDMA request is ser-
viced. If this bit is set to 1, EDMA requests are prioritized over CPU accesses.
When an L1P and L1D access collide, the L1P request is always given priority.
When an L2 location is operating as mapped RAM, an access to that location
operates like a standard RAM. A read request reads the value stored in that
location and a write request updates that location with the new data. When
an L2 location is enabled as a cache, the operation is similar to the L1D cache.
If a read request is made to the L2, the tag RAM for each of the cached blocks
is searched for that address. If a tag hit occurs, that data is sent to the request-
or. If the data is not in the L2 the requestor is stalled and the data is requested
from the Enhanced DMA. To fulfill an L1P request, the L2 controller must make
eight 64 bit requests to the EDMA. Similarly, four requests to the EDMA are
required to service an L1D request.
TMS320C6211/C6711 Two-Level Internal Memory
L2 Description
4-15