Texas Instruments TMS320C6201 Reference Manual page 350

Data Transmission and Reception
11.3.4.8 Multiphase Frame Example: AC97
Figure 11–14. AC97 Dual-Phase Frame Format
P1E1
FS(R/X)
1-bit data delay
D(R/X)
† PxEy denotes phase x and element y.
11-32
Figure 11–14 shows an example of the Audio Codec '97 (AC97) standard,
which uses the dual-phase frame feature. The first phase consists of a single
16-bit element. The second phase consists of 12 20-bit elements. The phases
are configured as follows:
(R/X)PHASE = 1b: specifying a dual-phase frame
(R/X)FRLEN1 = 0b: specifying one element per frame in phase 1
(R/X)WDLEN1 = 010b: specifying 16 bits per element in phase 1
(R/X)FRLEN2 = 0001011b: specifying 12 elements per frame in phase 2
(R/X)WDLEN2 = 011b: specifying 20 bits per element in phase 2
CLK(R/X)P = 0: specifying that the receive data sampled on the falling edge
of CLKR and the transmit data are clocked on the rising edge of CLKX
FS(R/X)P = 0: indicating that active frame sync signals are used
(R/X)DATDLY = 01b: indicating a data delay of one bit clock
P2E1 P2E2 P2E3 P2E4
16 bits
20 bits
Figure 11–14 shows the AC97 timing near frame synchronization. First the
frame sync pulse itself overlaps the first element. In McBSP operation, the inac-
tive-to-active transition of the frame synchronization signal actually indicates
frame synchronization. For this reason, frame synchronization can be high for
an arbitrary number of bit clocks. Only after the frame synchronization is recog-
nized as inactive and then active again is the next frame synchronization recog-
nized.
In Figure 11–15, there is 1-bit data delay. Regardless of the data delay, trans-
mission can occur without gaps. The last bit of the previous (last) element in
phase 2 is immediately followed by the first data bit of the first element in phase
1 of the next data frame.
{
P2E5 P2E6 P2E7 P2E8 P2E9 P2E10 P2E11 P2E12