Table of Contents
Advertisement
McBSP Interface Signals and Registers
11-4
Data is communicated to devices interfacing to the McBSP via the data transmit
(DX) pin for transmission and the data receive (DR) pin for reception. Control
information (clocking and frame synchronization) is communicated via CLKX,
CLKR, FSX, and FSR. The 'C6201/C6701 communicates to the McBSP via
32-bit-wide control registers accessible via the internal peripheral bus (see sec-
tion 2.7, Peripheral Bus ). Either the CPU or the DMA controller reads the re-
ceived data from the data receive register (DRR) and writes the data to be trans-
mitted to the data transmit register (DXR). Data written to the DXR is shifted out
to DX via the transmit shift register (XSR). Similarly, receive data on the DR pin
is shifted into the receive shift register (RSR) and copied into the receive buffer
register (RBR). RBR is then copied to DRR, which can be read by the CPU or
the DMA controller. This allows simultaneous internal data movement and ex-
ternal data communications.
The data receive and transmit registers (DRR and DXR) are mapped to loca-
tions shown in Table 11–2. For the TMS320C6211/C6711 device, the DRR and
DXR are also mapped to memory locations 30000000h–33FFFFFFh (McBSP
0) and 34000000h–3FFFFFFFh (McBSP 1), as shown in Table 11–3. Both the
CPU and the EDMA in the TMS320C6211/C6711 device can access the DRR
and DXR in all the memory-mapped locations shown in Table 11–3. A write to
any location in 30000000h – 33FFFFFFh is equivalent to a write to the DXR
of
McBSP
0
at
30000000h–3FFFFFFh is equivalent to a read from the DRR of McBSP 0 at
018C0000h. Similarly, a read from any location in 34000000h–3FFFFFFFh is
equivalent to a read from the DRR of McBSP 1 at 01900000h, while a write to
any location in 34000000h–3FFFFFFFh is equivalent to a write to the DXR of
McBSP 1 at 01900004h. You have a choice of reading from/writing to the DRR
and DXR in either the 3xxxxxxxh or the 018Cxxxxh/0190xxxxh location. Ac-
cesses to the 018Cxxxxh and 0190xxxxh locations go through the peripheral
bus. Therefore, it is recommended that you set up the EDMA to use the
3xxxxxxxh addresses for serial port servicing in order to free up the peripheral
bus for other functions. The McBSP control registers are only mapped to the
018Cxxxxh/0190xxxxh locations.
The remaining registers accessible to the CPU configure the control mechanism
of the McBSP. The McBSP registers are listed in Table 11–2. The control block
consists of internal clock generation, frame-synchronization signal generation
and control of these signals, and multichannel selection. This control block
sends notification of important interrupts to the CPU and events to the DMA
controller via the four signals shown in Table 11–4.
018C0004h.
A
read
from
any
location
in
Advertisement
Chapters
Table of Contents
