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Expansion Bus Host Port Operation
8-42
If the expansion bus host port operates in the asynchronous mode, every
transaction initiated by the host on the expansion bus is a two step process.
The host first has to set the XBISA register, and then transfer the data to/from
the address pointed to by the XBISA register. The data transfer can take place
with or without auto-incrementing the XBISA register. Whether or not the XBI-
SA gets auto-incremented is determined by AINC bit-field in bit one of the XBI-
SA register.
In order to read/write from the 'C6202 memory spaces, the host must follow
the following sequence:
1) Host writes address to the XBISA register, and sets AINC accordingly in
bit one of XBISA.
2) Host reads/writes to/from the address specified by the XBISA register.
Read or write is dictated by the XW/R signal. The XBISA register is auto-in-
cremented or not depending on what is written to the AINC bit during step
1.
If the expansion bus host port is configured to operate in asynchronous mode
the XCS signal is used for four purposes:
3) To select the expansion bus host port as a target of an external master.
4) On a read, the falling edge of XCS initiates read accesses.
5) On a write, the rising edge of XCS initiates write accesses.
6) The XCS falling edge latches expansion bus host port control inputs in-
cluding: XW/R and XCNTL.
The XRDY signal of the 'C6202 functions differently than the 'C6201 HPI
READY signal. The XRDY signal indicates normally not ready condition (ac-
tive low READY signal is internally OR-ed with XCS signal in order to obtain
XRDY).
Read and write timing diagrams for asynchronous the expansion bus host port
operation in the asynchronous mode are shown in Figure 8–24.
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