Texas Instruments TMS320C6201 Reference Manual page 62

Memory Mapped Operation
3.2 Memory Mapped Operation
Table 3–3. Internal Program RAM Address Mapping in Memory Mapped Mode
Block 0
Block 1
3-4
When the PCC field of the CPU control status register is programmed for
Mapped mode, both blocks of internal program RAM are mapped into internal
program space. Table 3–3 shows the address space for both blocks of RAM
for the map mode selected at device reset.
0140 0000h – 0141 FFFFh
0142 0000h – 0143 FFFFh
In mapped mode, both the CPU and the DMA can access all locations in both
blocks of RAM. Any access outside of the address space that the internal RAM
is mapped to is forwarded to the EMIF. The DMA can only access one of the
two blocks of RAM at a time. The CPU and DMA can access the internal RAM
without interference as long as each accesses a different block. If the CPU and
DMA attempt to access the same block of RAM at the same time, then the DMA
is stalled until the CPU completes its accesses to that block. After the CPU ac-
cess is complete, the DMA is allowed to access the RAM. The DMA cannot
cross between Block 0 and Block 1 in a single transfer. You must use separate
DMA transfers to cross block boundaries.
Map 0 Map 1
0000 0000h – 0x0001 FFFFh
0002 0000h – 0x0003 FFFFh