Texas Instruments TMS320C6201 Reference Manual page 348

Data Transmission and Reception
11.3.4.7 Data Delay: (R/X)DATDLY
Figure 11–12. Data Delay
CLK(R/X)
FS(R/X)
D(R/X)
data delay 0
D(R/X)
data delay 1
D(R/X)
data delay 2
11-30
The start of a frame is defined by the first clock cycle in which frame synchro-
nization is active. The beginning of actual data reception or transmission with
respect to the start of the frame can be delayed if required. This delay is called
data delay. RDATDLY and XDATDLY specify the data delay for reception and
transmission, respectively. The range of programmable data delay is zero to
two bit clocks ((R/X)DATDLY = 00b to10b), as indicated in Table 11–7 and
shown in Figure 11–12. Typically, a 1-bit delay is selected because data often
follows a 1-cycle active frame sync pulse.
0-bit period
B7
1-bit period
2-bit period
Normally a frame sync pulse is detected or sampled with respect to an edge of
serial clock CLK(R/X). Thus, on a subsequent cycle (depending on data delay
value), data can be received or transmitted. However, in the case of a 0-bit data
delay, the data must be ready for reception and/or transmission on the same
serial clock cycle. For reception, this problem is solved by receive data being
sampled on the first falling edge of CLKR when an active (high) FSR is detected.
However, data transmission must begin on the rising edge of CLKX that gener-
ated the frame synchronization. Therefore, the first data bit is assumed to be in
the XSR and DX. The transmitter then asynchronously detects the frame syn-
chronization, FSX goes active, and it immediately starts driving the first bit to be
transmitted on the DX pin.
B6 B5
B7 B6
B7
B4 B3
B5 B4
B6 B5