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Programmable Clock and Framing
11.5.3.1 Frame Period and Frame Width: FPER and FWID
Figure 11–42. Programmable Frame Period and Width
1
2
CLKG
FSG
11.5.3.2 Receive Frame Sync Selection: DLB, FSRM, GSYNC
11-62
The FPER block is a 12-bit down counter that can count down the generated
data clocks from 4095 to 0. FPER controls the period of active frame sync
pulses. The FWID block in the sample rate generator is an 8-bit down counter.
The FWID field controls the active width of the frame sync pulse.
When the sample rate generator comes out of reset, FSG is in an inactive (low)
state. After this, when FRST = 1 and FSGM = 1, frame sync signals are gener-
ated. The frame width value (FWID + 1) is counted down on every CLKG cycle
until it reaches 0 when FSG goes low. Thus, the value of FWID+1 determines
an active frame pulse width ranging from 1 to 256 data bit clocks. At the same
time, the frame period value (FPER + 1) is also counting down, and when this
value reaches 0, FSG goes high again, indicating a new frame is beginning.
Thus, the value of FPER + 1 determines a frame length from 1 to 4096 data
bits. When GSYNC = 1, the value of FPER does not matter. Figure 11–42
shows a frame of 16 CLKG periods (FPER = 15 or 00001111b).
3
4
5
6
7
Frame period: (FPER + 1)
Frame width: (FWID + 1)
Table 11–17 explains how you can select various sources to provide the re-
ceive frame synchronization signal. Note that in digital loopback mode (DLB
= 1) the transmit frame sync signal is used as the receive frame sync signal
and that DR is internally connected to DX.
8
9
10
11
12
CLKG
CLKG
13
14
15
16
17
18
19
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