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Figure 15–10. EMU0/1 Configuration With Additional AND Gate to Meet Timing
Requirements
XCNT_ENABLE
PAL
TCK
Circuitry required for >25-ns rising/
falling edge modification
To Emulator EMU1
Notes:
1) The low time on EMUx–IN should be at least one TCK cycle and less than 10 s. Software will set the EMUx–OUT
pin to a high state.
2) To enable the open-collector driver and pullup resistor on EMU1 to provide rising/falling edges of less than 25 ns,
the modification shown in this figure is suggested. Rising edges slower than 25 ns can cause the emulator to detect
false edges during the RUNB command or when the external counter selected from the debugger analysis menu
is used.
Figure 15–11. Suggested Timings for the EMU0 and EMU1 Signals
TCK
EMU0/1-OUT
EMU0/1-IN
Backplane
EMU0/1-IN
Pullup
Resistor
EMU0/1-OUT
To Emulator EMU0
EMU1
AND
Up to
m boards
Emulation Design Considerations
Pullup Resistor
Open
Collector
Drivers
Device
1
Pullup Resistor
Open
Collector
Drivers
Device
1
EMU1 signal from other boards
Designing for JTAG Emulation
Target Board 1
EMU0/1
Device
. . .
n
Target Board m
EMU0/1
Device
. . .
n
15-21
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