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Functional Overview
3.3.1 DMA Channel Control Register (DMA_CCR)
The channel control register (DMA_CCR) bit layouts are shown in Figure 3−5.
15
14
DST AMODE
R/W, 00
7
6
EN
PRIO
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
The SYNC[4:0] bits specify the event that can initiate the DMA transfer for the corresponding DMA channel.
The five bits allow several configurations as listed in Table 3−4. The bits are set to zero upon reset. For those
synchronization modes with more than one peripheral listed, the Serial Port Mode bit field of the External Bus
Selection Register dictates which peripheral event is actually connected to the DMA input.
SYNC FIELD IN
DMA_CCR
00000b
No event synchronized
00001b
McBSP 0 Receive Event (REVT0)
00010b
McBSP 0 Transmit Event (XEVT0)
00011b
Reserved. These bits should always be written with 0.
00100b
Reserved. These bits should always be written with 0.
McBSP1/MMC−SD1 Receive Event
Serial Port 1 Mode:
00101b
00 = McBSP1 Receive Event (REVT1)
01 = MMC/SD1 Receive Event (RMMCEVT1)
10 = Reserved
11 = Reserved
McBSP1/MMC−SD1 Transmit Event
Serial Port 1 Mode:
00110b
00 = McBSP1 Transmit Event (XEVT1)
01 = MMC/SD1 Transmit Event (XMMCEVT1)
10 = Reserved
11 = reserved
00111b
Reserved. These bits should always be written with 0.
01000b
Reserved. These bits should always be written with 0.
McBSP2/MMC−SD2 Receive Event
Serial Port 2 Mode:
00 = McBSP2 Receive Event (REVT2)
01001b
01 = MMC/SD2 Receive Event (RMMCEVT2)
10 = Reserved
11 = Reserved
† The I 2 C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the
DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization.
38
SPRS163H
13
12
SRC AMODE
R/W, 00
5
4
FS
R/W, 0
Figure 3−5. DMA_CCR Bit Locations
Table 3−4. Synchronization Control Function
SYNCHRONIZATION MODE
11
10
END PROG
Reserved
R/W, 0
R, 0
SYNC
R/W, 00000
April 2001 − Revised January 2008
9
8
REPEAT
AUTO INIT
R/W, 0
R/W, 0
0
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