The Expansion Bus Interface In The Tms320C6202 Block Diagram - Texas Instruments TMS320C6201 Reference Manual

Overview
Figure 8–2. The Expansion Bus Interface in the TMS320C6202 Block Diagram
External
memory
interface
(EMIF)
Timer 0
Timer 1
Multi-channel
buffered
serial port 0
(McBSP 0)
Multi-channel
buffered
serial port 1
(McBSP 1)
Expansion
bus
8-4
C6202 digital signal processor
Program bus
Direct memory access
controller (DMA)
Internal program memory
Program
access/
cache
controller
C6200B CPU
Instruction fetch
Instruction dispatch
Instruction decode
Data path A
A register file
.L1 .S1 .M1 .D1
1
Data access
controller
Power down
logic
1 block program/cache 1
block mapped program
(128k bytes each)
(256k bytes total)
Interrupt control
Control registers
In-circuit emulation
Data path B
B register file
.D2 .M2 .S2 .L2
2
Internal data
memory
(128k bytes)
2 blocks
4 blocks
each