Texas Instruments TMS320C6201 Reference Manual page 316

Boot Configuration
10.3.2 Memory at Reset Address
10.3.3 Boot Processes
10-8
For 'C6000 processors with multiple memory maps, the boot configuration
determines the type of memory located at the reset address for processor
operation, address 0 as shown in Table 10–1. When the BOOTMODE [4:0]
pins select MAP 1, this memory is internal. When the device mode is in MAP
0, the memory is external. When external memory is selected, BOOTMODE
[4:0] also determine the type of memory at the reset address. These options
effectively provide alternative reset values to the appropriate EMIF control reg-
isters.
The 'C6211/C6711 always has internal RAM at address 0, regardless of the
BOOTMODE[4:0] configuration.
The boot process is determined by the BOOTMODE[4:0] pins, as shown in
Table 10–1. Up to three types of boot processes are available:
No boot process: The CPU begins direct execution from the memory lo-
cated at address 0. If SDRAM is used in the system, the CPU is held until
SDRAM initialization is complete. This feature is not available on the
'C6211/C6711.
ROM boot process: The program located in external ROM is copied to ad-
dress 0 by the DMA/EDMA controller. Although the boot process begins
when the device is released from external reset, this transfer occurs while
the CPU is internally held in reset. This boot process also lets you choose
the width of the ROM. In this case, the EMIF automatically assembles con-
secutive 8-bit bytes or 16-bit halfwords to form the 32-bit instruction words
to be moved. These values are expected to be stored in little endian format
in the external memory, typically a ROM device.
The transfer is automatically done by the DMA/EDMA as a single-frame
block transfer from the to ROM address 0.
After completion of the block transfer, the CPU is removed from reset and
allowed to run from address 0.
The ROM boot process differs slightly between specific 'C6000 devices.
J
'C6201,'C6202,'C6701: The DMA copies 32K bytes from CE1 to
address 0, using default ROM timings. After the transfer the CPU
begins executing from address 0.
J
'C6211, 'C6711: THE EDMA copies 1K bytes from the beginning of
CE1 to address 0, using default ROM timings. After the transfer the
CPU begins executing from address 0.