Texas Instruments TMS320C6201 Reference Manual page 371

Tms320c6000 series peripherals
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11.5 Programmable Clock and Framing
Figure 11–37. Clock and Frame Generation
CLKXM
CLKX pin
CLKXP
CLKRP
CLKRM
CLKR pin
CLKRP
internal clock source
FSR_int
CLKS pin
Inset:
(R/X) IOEN
Yyy_int
† 'C6201/C6202/C6701 uses CPU clock as the internal clock source to the sample rate generator.
'C6211/C6711 uses CPU/2 clock as the internal clock source to the sample rate generator.
The McBSP has several means of selecting clocking and framing for both the
receiver and transmitter. Clocking and framing can be sent to both portions by
the sample rate generator. Each portion can select external clocking and/or
framing independently. Figure 11–37 is a block diagram of the clock and frame
selection circuitry.
Clock selection
CLKXP
See inset
CLKX_int
0
1
CLKXM
See inset
1
0
0
1
DLB
CLKRM
CLKR_int
CLKG
FSXP
See inset
FSX_int
0
Transmit
1
FSXM
FSGM
See inset
1
Receive
0
0
1
DLB
FSR_int
FSRM
FSG
Sample
rate
generator
Multichannel Buffered Serial Ports
Programmable Clock and Framing
Frame selection
FSXM
FSXP
DXR to XSR
0
FSRP
FSRM & GSYNC
1
FSRP
FSX pin
FSR pin
11-53

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