Texas Instruments TMS320C6201 Reference Manual page 339

11.3.2 Determining Ready Status
11.3.2.1 Receive Ready Status: REVT, RINT, and RRDY
Alternatively, on either write (steps 1 and 5 above), the transmitter and receiver
can be placed in or taken out of reset individually by modifying only the desired
bit. The necessary duration of the active(low) period of XRST or RRST is at least
two bit clocks (CLKR/CLKX). This procedure for reset initialization can be ap-
plied generally when the receiver or transmitter has to be reset during its normal
operation and also when the sample rate generator is not used for either op-
eration. The sample-rate generator reset procedure is explained in section
11.5.1.2.
Notes:
1) The appropriate fields in the serial port configuration registers SPCR,
PCR, RCR, XCR, and SRGR should be modified only when the affected
portion of the serial port is in reset.
2) The data transmit register, DXR, should be loaded by the CPU or DMA
only when the transmitter is not in reset (XRST = 1). The exception to this
rule occurs during non-digital loop-back mode, which is described in sec-
tion 11.4.1.
3) The multichannel selection registers MCR, XCER, and RCER can be
modified at any time as long as they are not being used by the current
block in the multichannel selection. See section 11.6.3.2 for more infor-
mation.
RRDY and XRDY indicate the ready state of the McBSP receiver and transmit-
ter, respectively. Writes and reads from the serial port can be synchronized by
any of the following methods:
Polling RRDY and XRDY
Using the events sent to the DMA controller (REVT and XEVT)
Using the interrupts to the CPU (RINT and XINT) that the events generate.
Note:
Note that reading the DRR and writing to DXR affects RRDY and XRDY, re-
spectively.
RRDY = 1 indicates that the RBR contents have been copied to the DRR and
that the data can be read by either the CPU or the DMA controller. Once that
Data Transmission and Reception
Multichannel Buffered Serial Ports 11-21