Texas Instruments TMS320C6201 Reference Manual page 118

Resource Arbitration and Priority Configuration
5.9 Resource Arbitration and Priority Configuration
5.9.1 DMA Auxiliary Control Register and Priority Between Channels
5-30
Priority decides which of competing requesters have control of a resource with
multiple requests. The requesters include:
The DMA channels
The CPU's program and data accesses
The resources include:
Internal data memory
Internal program memory
The internal peripheral registers, which are accessed through the peripher-
al bus
External memory, accessed through the external memory interface
(EMIF)
Expansion memory, accessed through the expansion bus
Two aspects of priority are programmable:
DMA versus CPU priority: Each DMA channel can be independently config-
ured in high-priority mode by setting the PRI bit in the associated DMA channel
primary control register. The AUXPRI field in the DMA auxiliary control register
allows the same feature for the auxiliary channel. When in high-priority mode,
the associated channel's requests are sent to the appropriate resource with
a signal indicating the high priority status. By default, all these fields are 0, dis-
abling the high-priority mode. Each resource can use this signal in its own
priority scheme for resolving conflicts. See to resource specific documentation
for information how a particular resource uses this signal.
Priority between DMA channels: The DMA controller has a fixed priority
scheme, with channel 0 having highest priority and channel 3 having lowest
priority. The auxiliary channel can be given a priority anywhere within this hier-
archy.
The fields in the DMA auxiliary control register affect the auxiliary channel. The
fields in this register are shown in Figure 5–12 and are summarized Table 5–9.