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TMS320C6211/C6711: The 'C6211/C6711 is a cache-based architecture,
with separate level-one program and data caches. These cache spaces are
not included in the memory map and are enabled at all times. The level-one
caches are only accessible by the CPU.
The level-one program cache (L1P) controller interfaces the CPU to the L1P.
A 256-bit wide path is provided from to the CPU to allow a continuous stream
of 8 32-bit instructions for maximum performance.
The level-one data cache (L1D) controller provides the interface between the
CPU and the L1D. The L1D is a dual-ported memory, which allows simulta-
neous access by both sides of the CPU.
On a miss to either L1D or L1P, the request is passed to the L2 controller. The
L2 controller facilitates:
The CPU and the enhanced direct memory access (EDMA) controller ac-
cesses to the internal memory, and performs the necessary arbitration
The CPU data access to the EMIF
The CPU accesses to on-chip peripherals
Sends request to EMIF for an L2 data miss
The internal SRAM of the 'C6211/C6711 is a unified program and data memory
space. The L2 memory space may be configured as all memory-mapped
SRAM, all cache, or a combination of the two.
Features and Options of the TMS320C6000 Devices
Overview of TMS320C6000 Memory
Introduction
1-7
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