Texas Instruments TMS320C6201 Reference Manual page 317

Host boot process: The CPU is held in reset while the remainder of the
device is released. During this period, an external host can initialize the
CPU's memory space as necessary through the host interface, including
external memory configuration registers. Once the host is finished with all
necessary initialization, it must set the DSPINT to complete the boot pro-
cess. This transition causes the boot configuration logic to remove the
CPU from its reset state. The CPU then begins execution from address 0.
The DSPINT condition is not latched by the CPU, because it occurs while
the CPU is still in reset. Also, DSPINT wakes the CPU from internal reset
only if the HPI boot process is selected. All memory may be written to and
read by the host. This allows for the host to verify what it sends to the proc-
essor, if required.
Note:
The host interface used during host boot varies between different devices,
as follows:
'C6201, 'C6701, 'C6211, 'C6711: The HPI is used for the host boot. The
HPI is always a slave interface, and needs no special configuration.
'C6202: The expansion bus is used for the host boot. The type of host
interface is determined by a set of latched signals during rest.
Boot Modes and Configuration
Boot Configuration
10-9