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Data Transmission and Reception
11.3 Data Transmission and Reception
11.3.1 Resetting the Serial Port: (R/X)RST, GRST, and RESET
11-18
As shown in Figure 11–1 on page 11-3, the receive operation is triple-buff-
ered and the transmit operation is double-buffered. Receive data arrives on
the DR and is shifted into the RSR. Once a full element (8, 12, 16, 20, 24, or
32 bits) is received, the RSR is copied to the receive buffer register (RBR) only
if the RBR is not full. The RBR is then copied to the DRR unless the DRR has
not been read by the CPU or the DMA controller.
Transmit data is written by the CPU or the DMA controller to the DXR. If there
is no data in the XSR, the value in the DXR is copied to the XSR. Otherwise,
the DXR is copied to the XSR when the last bit of data is shifted out on the DX.
After transmit frame synchronization, the XSR begins shifting out the transmit
data on the DX.
The serial port can be reset in the following two ways:
Device reset (RESET pin is low) places the receiver, the transmitter, and
the sample rate generator in reset. When the device reset is removed
(RESET = 1), FRST = GRST = RRST = XRST = 0, keeping the entire serial
port in the reset state.
The serial port transmitter and receiver can be independently reset by the
XRST and RRST bits in the SPCR. The sample rate generator is reset by
the GRST bit in the SPCR.
Table 11–8 shows the state of the McBSP pins when the serial port is reset by
these methods.
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