Texas Instruments TMS320C6201 Reference Manual page 165

Figure 6–19. QDMA Pseudo Registers
31
QDMA_S_OPT
31
QDMA_S_SRC
31
QDMA_S_CNT
31
QDMA_S_DST
31
QDMA_S_IDX
Figure 6–20. QDMA Options Register (QDMA_OPT, QDMA_S_OPT)
31 29 28 27
PRI ESIZE 2DS
RW, +0 RW, +0 RW, +0
Arrary/frame count
Arrary/frame index
The QDMA options register shown in Figure 6–20 is similar to the options
parameter in the EDMA parameter RAM, which is shown in Figure 6–8 and
described in Table 6–3. All fields in the registers function identically to the
corresponding EDMA transfer parameters. Refer to section 6.6 and the
corresponding sections for details. However, the QDMA does not support
parameter updates (e.g. element count reload), or transfer event linking. Since
the QDMA does not support transfer event linking, bit 1 of the QDMA_OPT
register is reserved, as opposed to the LINK bit-field in the EDMA options
parameter.
26 25 24 23
SUM 2DD
RW, +0 RW, +0
Although the QDMA mechanism does not support event linking, it supports
completion interrupts, as well as QDMA chaining with EDMA events. The
QDMA_OPT and the QDMA_S_OPT registers include the same TCINT and
TCC fields as the EDMA options parameter. QDMA completion interrupts are
enabled and set in the same way as EDMA completion interrupts. To set a
QDMA completion interrupt, the user needs to set TCINT to '1' and program
the transfer completion code field (TCC) to specify the interrupt desired. The
QDMA options
SRC address
16 15
Element count
DST address
16 15
Element index
22 21 20 19
DUM TCINT
RW, +0 RW, +0 RW, +0
Quick DMA (QDMA)
0
0
0
0
0
16 15
TCC Reserved
R,+0
EDMA Controller
0200 0020h
0200 0024h
0200 0028h
0200 002Ch
0200 0030h
1 0
FS
RW,+0
6-39