Texas Instruments TMS320C6201 Reference Manual page 42

DMA Controller Access to Program Memory
2.3 DMA Controller Access to Program Memory
2-6
The DMA controller can read and write to internal program memory when the
memory is configured in mapped mode. The CPU always has priority over the
DMA controller for access to internal program memory regardless of the value
of the PRI bit for that DMA channel. DMA controller accesses are postponed
until the CPU stops making requests. To avoid losing future requests that occur
after arbitration and while a DMA controller access is in progress, the CPU in-
curs one wait state per DMA controller access. The maximum throughput to the
DMA is one access every other cycle. In a cache mode, a DMA controller write
is ignored by the program memory controller, and a read returns an undefined
value. For both DMA reads and writes in cache modes, the DMA controller is
signaled that its request has finished. At reset, the program memory system is
in mapped mode, allowing the DMA controller to boot load code into the internal
program memory.
See Chapter 7, TMS320C6000 Boot Modes, for more information on bootload-
ing code.