Texas Instruments TMS320C6201 Reference Manual page 438

JTAG Emulator Cable Pod Logic
15.4 JTAG Emulator Cable Pod Logic
Figure 15–2. JTAG Emulator Cable Pod Interface
GND (Pins 4,6,8,10,12)
EMU0 (Pin 13)
EMU1 (Pin 14)
TCK_RET (Pin 9) {
PD(V CC ) (Pin 5)
15-4
Figure 15–2 shows a portion of the emulator cable pod. These are the func-
tional features of the pod:
Signals TDO and TCK_RET can be parallel-terminated inside the pod if
required by the application. By default, these signals are not terminated.
Signal TCK is driven with a 74LVT240 device. Because of the high-current
drive (32 mA I
OL
to TCK_RET, then you can use the parallel terminator in the pod.
Signals TMS and TDI can be generated from the falling edge of TCK_RET,
according to the IEEE 1149.1 bus slave device timing rules.
Signals TMS and TDI are series-terminated to reduce signal reflections.
A 10.368-MHz test clock source is provided. You may also provide your
own test clock for greater flexibility.
180 Ω
TDO (Pin 7)
10.368 MHz
180 Ω
† The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided
as an optional target system test clock source.
/I ), this signal can be parallel-terminated. If TCK is tied
OH
+5 V
74F175
270 Ω
JP1
D
74LVT240
A
74AS1034
+5 V
270 Ω
JP2
100 Ω
RESIN
Q
Q
33 Ω
Y TMS (Pin 1)
33 Ω
Y
Y
TDI (Pin 3)
Y
TCK (Pin 11) {
TRST (Pin 2)
74AS1004
TL7705A